This specification refers to embodiments of semiconductor devices having a body region and a depletable region which adjoins the body region, and a method for manufacturing a semiconductor device. In one or more embodiments, the present specification pertains to power semiconductor devices such as unipolar devices, for example, field effect devices, having an electrode structure arranged next to a body region and a depletable region.
Unipolar devices such as MOSFETs are used in switching applications, such as, for example, switching power supplies. MOSFETs are suited to such switching applications due to their relatively high switching speed and low control power requirements. However, they exhibit dynamic losses which represent a large percentage of the total losses in many applications. The dynamic losses are directly proportional to the device rise and fall times which are, in turn, proportional to the gate-drain capacitance, i.e. the Miller capacitance, of the device (CGD or QGD).
As illustrated in FIG. 12, the Miller capacitance of a MOSFET also results in a “flat” region in the gate curve of conventional MOSFETs. This flat region, referred to as Miller region, is representative of the device transitioning from a blocking state to a conducting state or from a conducting state to a blocking state. In FIG. 12, a transition from a blocking to a conductive state is illustrated. The dashed line represent the case that the drain-source voltage UDS is zero.
In the Miller region most of the switching losses occur since the device current and voltage are high. In addition to the switching losses, the Miller capacitance may also contribute to significant oscillations in the gate and load circuits during switching which could adversely affect the device performance and could even lead to a destruction of the device. Adjusting the Miller capacitance is therefore an ongoing desire.
For reducing the switching losses, the area over which the gate and drain regions overlap could be reduced. Different thereto, an increase of the Miller capacitance might be desired to reduce the slope of the voltage increase or decrease to damp excitation of oscillations during switching. Another approach would be to increase the internal gate resistance by changing the layout design of the gate electrode structure. Increasing the internal gate resistance leads, however, to higher switching losses. Furthermore, by changing the layout design, the initial capacitances CGS and CGD and hence the gate charge is changed which affects the losses in the respective drive circuits.
For these and other reasons, there is a need for the present invention.